An analog-to-digital conversion circuit (hereinafter, referred to as “ADC”) that is a typical example of an analog digital conversion apparatus has various circuits including a comparator used for voltage comparison. Therefore, if an offset voltage is generated between comparison voltages due to variation in transistor characteristics or asymmetric circuit layout, there is a concern that correct comparison results cannot be obtained, which would negatively affect the operation of the ADC.
Then, an ADC having a function to perform control so as to cancel the offset voltage generated in the comparator has been proposed. For example, as a parallel comparison system (also called as a “flash type”) ADC, an ADC having a circuit that performs control so as to cancel the offset voltage generated in the comparator based on the output signal of the comparator has been proposed (for example, see Patent Document 1, Non-patent Documents 1 and 2). Hereinafter, a circuit that performs control so as to cancel the offset voltage is simply referred to as an OFC circuit (offset cancel circuit). In an ADC of the parallel comparison system having an OFC circuit, the OFC circuit is provided for every comparator, and the corresponding comparators and OFC circuits are connected by signal lines respectively.    [Patent Document 1] Japanese Laid-open Patent Publication No. 2000-165241    [Non-patent Document 1] Chun-Ying Chen, Michael Le, Kwang Young Kim ┌A Low Power 6-bit Flash ADC with Reference Voltage and Common-Mode Calibration┘2008 Symposium on VLSI Circuits Digest of Technical Papers p. 12-13[Non-patent Document 2] Yuko Tamba, Kazuo Yamakido ┌A COMS 6b 500MSample/s ADC for a Hard Disk Drive Read Channel┘ 1999 IEEE International Solid-State Circuits Conference p. 324-325, 474 ISSCC99/SESSION 18/PAPER WA 18.5
In an ADC of the parallel comparison method, assuming the number of bits of an output digital signal as n, 2n−1 units of comparators are required. Therefore, in an ADC in the parallel comparison method having an OFC circuit, assuming the number of bits of digital signal as n, 2n−1 units of comparators are required, so 2n−1 lines of the signal lines connecting the corresponding comparators and the OFC circuits respectively are also required. For example, assuming the number of bits of the digital signal as 4, 15 units of comparators are required, so the 15 lines of signal lines connecting the corresponding comparators and OFC circuits are required.
Therefore, in the parallel comparison method having an OFC circuit, when the number of bits of the digital signal is increased by 1, approximately twice the number of units of signal lines connecting the corresponding comparators and OFC circuits respectively are required.
As described above, an attempt to increase the number of bits of the digital signal in an ADC of the parallel comparison system having OFC circuits increases the number of lines connecting the corresponding comparators and OFC circuits respectively, and the circuit becomes crowded as a result.